The present invention relates generally to semiconductor device design and, more particularly, to a structure for optimized isolation of devices formed within a semiconductor integrated circuit (“IC”).
In advanced complementary metal oxide semiconductor (“CMOS”) technology, noise isolation and the elimination of latch-up are becoming increasingly important. More particularly, as MOS field effect transistor (“MOSFET”) threshold voltages decrease, the need to isolate circuitry from RF noise sources has become more important. This has led to an increased use of “isolated” MOSFETS or “triple-well technology” MOSFETS.